FIG. 1 (Prior Art) is a circuit diagram of an SRAM cell. The SRAM cell 2 is comprised of a first resistor (impedance) R1, a second resistor (impedance) R2, a first MOS transistor T1, a second MOS transistor T2, a third MOS transistor T3 and a fourth MOS transistor T4. The first resistor R1, the first MOS transistor T1 and the second resistor R2, the second MOS transistor T2 are serially connected between a first voltage source and a second voltage source (for example, between a voltage source V.sub.DD and ground V.sub.SS). The gate of the first MOS transistor T1 is connected to a second node B. The gate of the second MOS transistor T2 is connected to a first node A. Besides, the third MOS transistor T3 is connected between a first bit line BL and the first node A. The gate of the third MOS transistor T3 is connected to a word line WL. And, the fourth MOS transistor T4 is connected between the second bit line BL and the second node B. The gate of the fourth MOS transistor T4 is connected to the word line WL.
When the first node A is at a high voltage level (like the voltage source V.sub.DD), the second MOS transistor T2 is turned on and the second node B is at a low voltage level (like ground V.sub.SS). Therefore, the first MOS transistor is turned off and the node A remains at a high voltage level. In addition, when the first node A is at a low voltage level (like ground V.sub.SS), the second MOS transistor T2 is turned off and the second node B is at a high voltage level (like the voltage source V.sub.DD). Therefore, the first MOS transistor T1 is turned on and the first node A remains at a low voltage level.
FIG. 2 (Prior Art) is an equivalent circuit diagram of the SRAM cell in FIG. 1. The SRAM cell 2 in FIG. 1 can be regarded as a flip-flop comprising the inverters I and II of FIG. 2. Voltage source Vn is the noise of the circuit. In addition, FIG. 3 (Prior Art) is a diagram of the voltage transfer characteristic of the circuit in FIG. 2. The largest square between two curves (a dotted square in FIG. 3) is the noise margin, which can be used for measuring the circuit immunity. Consequently, the processing and yielding of a logic circuit can be greatly improved with reference of the noise margin measured.
FIG. 4 (Prior Art) is a diagram of the layout of a conventional SRAM. An active region 12 is defined by a field oxide layer 10 on a P-type semiconductor substrate 1. Polysilicon layers 142, 144, 146 are then dielectrically and selectively formed on the field oxide layer 10 and the active region 12. In this case, the polysilicon layer 142 is regarded as the gate of the first MOS transistor T1, the polysilicon layer 144 is regarded as the gate of the second MOS transistor T2, in addition, the polysiliconn layer 146 is regarded as the gate of the third MOS transistor T3, and the gate and the word line WL of the fourth MOS transistor T4. Further, N+ diffusion regions are doped in the active region 12 so as to form the drains and the sources of the first MOS transistor through the fourth MOS transistor T1, T2, T3, T4. The polysilicon layer 142 is coupled to the second MOS transistor T2 and the fourth MOS transistor T4 via buried contact so as to form the second node B. The polysilicon layer 144 is coupled to the first MOS transistor T1 and the third MOS transistor T3 via buried contact so as to form the first node A. For clarity, the first resistor R1 and the second resistor R2 are not shown in FIG. 4, and can be formed on the first MOS transistor through the fourth MOS transistor T1, T2, T3, T4 by polysilicon layers. Besides, the first and the second bit line BL, BL made of metal are formed on the first resistor R1 and the second resistor R2 so as to couple the third MOS transistor T3 and the fourth MOS transistor T4 via buried contact 182, 184.
In this embodiment, since the layout of the SRAM in FIG. 4 is comprised of a matrix, the SNM measurement can not be obtained through the first node A and the second node B. That is, the efficiency and the yield of the process can not be elevated.